Publications
Research spanning AI systems, accelerator architecture, compute-in-memory, and hardware-software co-design.
2026
Charon: A Unified and Fine-Grained Simulator for Large-Scale LLM Training and Inference
Charon is a unified, modular simulator for both large-scale LLM training and inference. Its operator-level graph model captures computation, communication, and parallelism choices with under 5.35% prediction error across evaluated systems, while enabling substantially cheaper design exploration than cluster profiling.
TACC: A 42.9 TOPS/W/mm² Ternary/INT/FP LLM Accelerator with Lossless Weight Compression
TACC combines lossless ternary-weight compression with decompress-free execution, symmetric Gray coding, and reconfigurable LUT tensor cores. Fabricated in 16 nm CMOS, it supports ternary, integer, FP8, and BF16 computation while reaching 42.9 TOPS/W/mm².
2025
Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training
Vorion integrates dedicated 3D Gaussian Splatting rendering and training into a RISC-V GPGPU with minimal changes to a conventional graphics pipeline. Z-tiling and a Gaussian/pixel-centric hybrid dataflow raise parallelism, enabling real-time rendering and accelerated training in a 16 nm prototype design.
GSAcc: Accelerate 3D Gaussian Splatting via Depth Speculation and Gaussian-Centric Rasterization
GSAcc restructures 3D Gaussian Splatting around depth speculation and a Gaussian-centric dataflow so preprocessing, sorting, and rasterization can overlap without storing large intermediate results. Dedicated sorting and rasterization units deliver up to 2.3× better PPA and 2.9× lower energy than the prior GSCore accelerator.
2024
Data Movement-Aware, Ping-Pong Ising Machine Supporting Full Connectivity and Variable Bitwidths
This compute-in-memory Ising machine keeps interaction coefficients stationary while a ping-pong transpose architecture limits spin movement to single-bit transfers. Full connectivity, configurable precision, and a compact bitcell-reference ADC improve solution time, power efficiency, and silicon area over prior designs.
CILP: An Arbitrary-Bit Precision All-Digital Compute-in-Memory Solver for Integer Linear Programming Problems
CILP repurposes foundry 8T SRAM for in-memory constraint checking, objective evaluation, and variable updates in integer linear programs. Its all-digital, arbitrary-precision compute unit preserves exact feasibility while reducing data movement, measured cycles, and energy relative to software solvers.
Vecim: A 289.13 GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing
Vecim turns a RISC-V vector register file into an all-digital compute-in-memory engine for INT8, BF16, and FP16 multiply-add operations. The measured 65 nm chip reduces register-file data movement and sustains up to 289.13 GOPS/W while retaining a programmable vector architecture.
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits
This AES core introduces intra-cycle timing and execution randomness while preserving synchronous round boundaries for straightforward SoC integration. Tunable replica circuits and stochastic module scheduling obscure power and electromagnetic signatures in a synthesizable, all-digital implementation.
2023
A 118 GOPS/mm² 3D eDRAM TensorCore Architecture for Large-Scale Matrix Multiplication
This architecture repurposes monolithic 3D eDRAM as a dense, reconfigurable matrix-multiplication fabric. A bit-stationary TensorCore dataflow supports INT8 and BF16 workloads, reaching 118 GOPS/mm² and improving compute density on NeRF and LLaMA-7B evaluations.
CIMGN: An Energy-Efficient All-Digital Compute-in-Memory Graph Neural Network Processor
CIMGN couples digital compute-in-memory transformation with a CAM-enabled search-reduce engine for irregular graph aggregation. Its multicore dataflows exploit sparsity and edge reuse, enabling complete GNN inference with scalable precision on a measured 65 nm prototype.
A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAM-Enabled Search-Reduce
This GNN accelerator uses a hybrid analog-digital compute-in-memory macro for feature transformation and a CAM search-reduce path for sparse neighborhood aggregation. Adaptive vertex- and edge-centric dataflows map irregular graph structure while preserving efficient dense computation.
Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems
Snap-SAT maps Boolean clauses and variables into reusable SRAM so clause evaluation and local variable updates occur directly in memory. The measured all-digital 65 nm prototype scales to hard SAT instances while providing large speed and energy gains over CPU and mobile software solvers.
2022
Ising-CIM: A Reconfigurable and Scalable Compute-Within-Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems
Ising-CIM reuses embedded-memory bitcells and peripheral circuits to perform analog Hamiltonian calculations directly on bitlines. A 65 nm silicon prototype demonstrates scalable max-cut optimization with compact spin area and up to 1091× faster annealing than a CPU implementation.
2021
Characterizing and Demystifying the Implicit Convolution Algorithm on Commercial Matrix-Multiplication Accelerators
This work explains a hardware-friendly implicit-im2col algorithm that dynamically lowers convolution onto GEMM engines without material memory or performance overhead. Measurements and simulation characterize its use on Google TPU-style systolic arrays and show that it also maps effectively to NVIDIA Tensor Cores.
NAAS: Neural Accelerator Architecture Search
NAAS jointly searches neural-network structure, accelerator connectivity, and compiler mappings in one optimization loop. By co-optimizing choices that earlier tools treated separately, it finds matched model-hardware designs with substantially lower energy-delay product and improved ImageNet accuracy.